H8 Emulation Help - 8080A Processor

8080A Processor Technical Documentation

This page briefly documents the 8080A processor. While the level of detail isn't enough to learn the 8080A cold, it should be a good refresher and reference for anyone who has programmed one in the past, using assembly language.

Another good reference would be the emu8080.c source code module, which has a (presumed correct) procedural implementation of each instruction. That is, at least, the definitive documentation of how this particular 8080A processor works.

There are four sections to this page:

Flag Byte - Describes the condition flag values and shows the layout of the condition flag byte as it would appear on the stack.
Register and Condition Values - Gives the binary subfield values for the various register names, register pair names and condition values. These are used in the instruction definitions.
Instructions - Shows each machine instruction, its mnemonic, opcode value, the position and type of each binary subfield, the numer of machine cycles expended, the condition flags affected, and a short description of the instruction.
Octal Reference Summary - A chart that will allow you to quickly convert from a mnemonic to an octal opcode value and back again.

Programming Table of Contents

Main Table of Contents

Flag Byte

There are five condition flags associated with the execution of instructions on the 8080A. They are Zero, Sign, Parity, Carry and Auxiliary Carry, and are each represented by a 1-bit register in the CPU. A flag is "set" by forcing the bit to 1; "reset" by forcing the bit to zero.

The format of the flag byte on the stack is:

A
C

Unless indicated otherwise, when an instruction affects a flag, it affects it in the following manner:

Flag	Description
S	Sign. If the most significant bit of the result of the operation has the value 1, this flag is set; otherwise it is reset.
Z	Zero. If the result of an instruction has the value of 0, this flag is set; otherwise it is reset.
AC	Auxiliary Carry. If the instruction caused a carry out of bit 3 and into bit 4 of the resulting value, the auxiliary carry is set; otherwise it is reset. This flag is affected by single precision additions, subtractions, increments, decrements, comparisons and logical operations, but is principally used with additions and increments preceeding a DAA (Decimal Adjust Accumulator) instruction.
P	Parity. If the modulo 2 sum of the bits of the result of the operation is 0, (i.e., if the result has even parity), this flag is set; otherwise it is reset (i.e., if the result has odd parity).
C	If the instruction resulted in a carry (from addition) or a borrow (from subtraction or a comparison) out of the high-order bit, this flag is set; otherwise it is reset.

The instruction list (below) will tell you which instructions alter which flags.

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Register and Condition Values

Individual instructions contain 2- and 3-bit binary subfields designating which registers are being operated on, or, in the branch group, which condition is being tested. These are labeled ddd (destination), sss (source), rp (register pair) and ccc (condition) in the instruction descriptions below.

The following table gives names to the binary values.

DDD, SSS	Register Name	RP	Register Pair	CCC	Condition
000	B	00	BC	000	NZ
001	C	01	DE	001	Z
010	D	10	HL	010	NC
011	E	11	SP, PSW	011	C
100	H			100	PO(dd)
101	L			101	PE(ven)
110	M			110	P(lus)
111	A			111	M(inus)

The register pair SP is used with LXI and DAD. The register pair PSW is used with PUSH and POP.

When referring to the BC and DE register pairs in an instruction, you will generally use only the letter B or D, though the Heath assembler accepts BC and DE as well.

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Instructions

This section describes all the instuctions in the 8080A instruction set. See above for the values to substitute for sss, ddd, rp, and ccc in the descriptions below. "nnn" refers to a non-register numeric value given by the instruction operand.

Data Transfer Group
	Mnemonic	Opcode	Cycles	Flags Affected	Description
	MOV r1,r2	01dddsss	5	none	Copies the contents of register r2 to r1.
	MOV M,r2	01110sss	7	none	Copies the contents of register r2 to the byte addressed by the (HL) register pair.
	MOV r1,M	01ddd110	7	none	Copies the contents of the byte addressed by the (HL) register pair to r1.
	MVI r1,data	00ddd110	7	none	The content of the 2nd byte of the instruction (immediate data) is copied into the named register.
	MVI M,data	00110110	10	none	The content of the 2nd byte of the instruction (immediate data) is copied into the byte addressed by the (HL) register pair.
	LXI rp,data	00rp0001	10	none	The content of byte 2 and 3 of the instruction (immediate data) is copied into the named register pair.
	LDA addr	00111010	13	none	The content of the memory byte addressed by bytes 2 and 3 of the instruction are copied to register A.
	STA addr	00110010	13	none	The content of register A is copied to the memory byte addressed by bytes 2 and 3 of the instruction.
	LHLD addr	00101010	16	none	The content of the word (16 bits) at the address in bytes 2 and 3 of the instruction are copied to the HL register pair.
	SHLD addr	00100010	16	none	The content of register pair HL are copied to the word (16 bits) at the address given in bytes 2 and 3 of the instruction.
	LDAX rp	00rp1010	7	none	The content of the byte at the address found in the register pair (BC or DE only) is copied to register A.
	STAX rp	01rp0010	7	none	The content of register A is copied to memory at the address found in the register pair (BC or DE only).
	XCHG	11101011	4	none	The contents of the HL and DE register pairs are swapped.
Arithmetic Group
	Mnemonic	Opcode	Cycles	Flags Affected	Description
	ADD r	10000sss	4	Z,S,P,C,AC	The register is added to register A.
	ADD M	10000110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair is added to register A.
	ADI data	11000110	7	Z,S,P,C,AC	Instruction byte 2 (immediate data) is added to register A.
	ADC r	10001sss	4	Z,S,P,C,AC	The register and the Carry flag are added to register A.
	ADC M	10001110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair and the Carry flag are added to register A.
	ACI data	11001110	7	Z,S,P,C,AC	Instruction byte 2 (immediate data) and the Carry flag are added to Register A.
	SUB r	10010sss	4	Z,S,P,C,AC	The register is subtracted from register A.
	SUB M	10010110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair is subtracted from register A.
	SUI data	10010110	7	Z,S,P,C,AC	Instruction byte 2 (immediate data) is subtracted from register A.
	SBB r	10011sss	4	Z,S,P,C,AC	The register and the Carry flag are subtracted from register A.
	SBB M	10011110	0	Z,S,P,C,AC	The byte addressed by the (HL) register pair and the Carry flag are subtracted from register A.
	SBI data	11011110	7	Z,S,P,C,AC	Instruction byte 2 (immediate data) and the Carry flag are subtracted from register A.
	INR r	00ddd100	4	Z,S,P,AC	The register is incremented. Note that Carry is not affected.
	INR M	00110100	10	Z,S,P,AC	The byte addressed by the (HL) register pair is incremented. Note that Carry is not affected.
	DCR r	00ddd101	4	Z,S,P,AC	The register is decremented. Note that Carry is not affected.
	DCR M	00110101	10	Z,S,P,AC	The byte addressed by the (HL) register pair is decremented. Note that Carry is not affected.
	INX rp	00rp0011	5	none	The register pair is incremented as a 16-bit number.
	DCX rp	00rp1011	5	none	The register pair is decremented as a 16-bit number.
	DAD rp	00rp1001	10	C	The register pair is added to the HL register pair.
	DAA	00100111	4	Z,S,P,C,AC	Register A is adjusted to form two BCD digits as follows: (1) If the value of the least significant 4 bits of register A is greater than 9 or if the AC flag is set, 6 is added to the accumulator. (2) If the value of the most significant 4 bits of register A is now greater than 9 or if the C flag is set, 6 is added to the most significant 4 bits of register A.
Logical Group
	Mnemonic	Opcode	Cycles	Flags Affected	Description
	ANA r	10100sss	4	Z,S,P,C,AC	The register is anded with register A.
	ANA M	10100110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair is anded with register A.
	ANI data	11100110	7	Z,S,P,C,AC	The 2nd byte of the instruction (immediate data) is anded with register A.
	XRA r	10101sss	4	Z,S,P,C,AC	The register is exclusive-or'd with register A.
	XRA M	10101110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair is exclusive-or'd with register A.
	XRI data	11101110	7	Z,S,P,C,AC	The 2nd byte of the instruction (immediate data) is exclusive-or'd with register A.
	ORA r	10110sss	4	Z,S,P,C,AC	The register is or'd with register A.
	ORA M	10110110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair is or'd with register A.
	ORI data	11110110	7	Z,S,P,C,AC	The 2nd byte of the instruction (immediate data) is or'd with register A.
	CMP r	10111sss	4	Z,S,P,C,AC	The register is subtracted from register A and the result discarded; register A remains unchanged. The flags are set based on the result of this subtraction.
	CMP M	10111110	7	Z,S,P,C,AC	The byte addressed by the (HL) register pair is subtracted from register A and the result discarded; register A remains unchanged. The flags are set based on the result of this subtraction.
	CPI data	11111110	7	Z,S,P,C,AC	The 2nd byte of the instruction (immediate data) is subtracted from register A and the result discarded; register A remains unchanged. The flags are set based on the result of this subtraction.
	RLC	00000111	4	C	The contents of register A are shifted left one bit. Both the low-order bit and flag C are set to the value shifted out of the high-order bit. (This is an 8-bit rotate into Carry.)
	RRC	00001111	4	C	The contents of register A are shifted right one bit. Both the high-order bit and flag C are set to the value shifted out of the low-order bit. (This is an 8-bit rotate into Carry.)
	RAL	00010111	4	C	The contents of register A are shifted left one bit. The low-order bit is set to the value of flag C. Flag C is set to the value shifted out of the high-order bit. (This is a 9-bit rotate through Carry.)
	RAR	00011111	4	C	The contents of register A are shifted right one bit. The high-order bit is set to the value of flag C. Flag C is set to the value shifted out of the low-order bit. (This is a 9-bit rotate through Carry.)
	CMA	00101111	4	none	The contents of register A are complemented: the 1 bits become 0 and the 0 bits become 1.
	CMC	00111111	4	C	The Carry flag is complemented.
	STC	00110111	4	C	The Carry flag is forced to 1.
Branch Group
	Mnemonic	Opcode	Cycles *	Flags Affected	Description
	JMP addr	11000011	10	none	Control is passed to the instruction at the given address.
	J(condition)	11ccc010	10	none	If the specified condition is true, control is passed to the instruction at the given address.
	CALL	11001101	17	none	The next instruction address is pushed on the stack. Then control passes to the instruction at the given address.
	C(condition)	11ccc100	11/17	none	If the specified condition is true, the next instruction address is pushed on the stack. Then control passes to the instruction at the given address.
	RET	11001001	5	none	Control is passed to the address that is popped from the stack.
	R(condition)	11ccc000	5/11	none	If the specified condition is true, control is passed to the address that is popped from the stack.
	RST n	11nnn111	11	none	The next instruction address is pushed onto the stack. Then control is passed to the instruction at address 'n' * 8. (The program counter is set to the value 0000 0000 00nn n000.)
	PCHL	11101001	5	none	The contents of register pair HL are copied to the program counter, effectively passing control to the instruction at the address in HL.
Stack, I/O and Machine Control Group
	Mnemonic	Opcode	Cycles	Flags Affected	Description
	PUSH rp	11rp0101	11	none	The named register pair is pushed onto the stack.
	POP rp	11rp0001	10	(note)	The named register pair is popped off of the stack.
	XTHL	11100011	18	none	The contents of the HL pair are swapped with the 16-bit value at the top of the stack.
	SPHL	11111001	5	none	The contents of the HL pair are copied into the SP pair.
	IN port	11011011	10	none	The port named in the 2nd byte of the instruction (immediate data) is read and the data placed in register A.
	OUT port	11010011	10	none	The data in register A is written to the port addressed in the 2nd byte of the instruction (immediate data).
	EI	11111011	4	none	The interrupt system is enabled, following the execution of the next instruction.
	DI	11110011	4	none	The interrupt system is disabled immediately.
	HLT	01110110	7	none	The processor is halted. This condition persists until the next interrupt.
	NOP	00000000	4	none	No operation is performed.

* Where there are two values for cycles, the first is for the false condition and the second for the true condition.

Note: A POP instruction naming the BC, DE, or HL register pairs has no effect on the flags. A POP instruction naming the PSW affects all flags.

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Octal Reference Summary

To convert from a mnemonic to an octal opcode:

find the mnemonic in the table;
write down the two digits in the left-hand column of the same row;
add the digit at the top of the same column.

Example: mnemonic MOV C,A is octal opcode 117.

To convert from an octal opcode to a mnemonic:

find the first two digits of the octal opcode in the left-hand column;
find the third digit of the octal opcode at the top;
use the mnemonic code at the intersection.

Example: octal opcode 064 is mnemonic INR M.

	0	1	2	3	4	5	6	7
00_	NOP	LXI B	STAX B	INX B	INR B	DCR B	MVI B	RLC
01_	---	DAD B	LDAX B	DCX B	INR C	DCR C	MVI C	RRC
02_	---	LXI D	STAX D	INX D	INR D	DCR D	MVI D	RAL
03_	---	DAD D	LDAX D	DCX D	INR E	DCR E	MVI E	RAR
04_	---	LXI H	SHLD	INX H	INR H	DCR H	MVI H	DAA
05_	---	DAD H	LHLD	DCX H	INR L	DCR L	MVI L	CMA
06_	---	LXI SP	STA	INX SP	INR M	DCR M	MVI M	STC
07_	---	DAD SP	LDA	DCX SP	INR A	DCR A	MVI A	CMC
	0	1	2	3	4	5	6	7
10_	MOV B,B	MOV B,C	MOV B,D	MOV B,E	MOV B,H	MOV B,L	MOV B,M	MOV B,A
11_	MOV C,B	MOV C,C	MOV C,D	MOV C,E	MOV C,H	MOV C,L	MOV C,M	MOV C,A
12_	MOV D,B	MOV D,C	MOV D,D	MOV D,E	MOV D,H	MOV D,L	MOV D,M	MOV D,A
13_	MOV E,B	MOV E,C	MOV E,D	MOV E,E	MOV E,H	MOV E,L	MOV E,M	MOV E,A
14_	MOV H,B	MOV H,C	MOV H,D	MOV H,E	MOV H,H	MOV H,L	MOV H,M	MOV H,A
15_	MOV L,B	MOV L,C	MOV L,D	MOV L,E	MOV L,H	MOV L,L	MOV L,M	MOV L,A
16_	MOV M,B	MOV M,C	MOV M,D	MOV M,E	MOV M,H	MOV M,L	HLT	MOV M,A
17_	MOV A,B	MOV A,C	MOV A,D	MOV A,E	MOV A,H	MOV A,L	MOV A,M	MOV A,A
	0	1	2	3	4	5	6	7
20_	ADD B	ADD C	ADD D	ADD E	ADD H	ADD L	ADD M	ADD A
21_	ADC B	ADC C	ADC D	ADC E	ADC H	ADC L	ADC M	ADC A
22_	SUB B	SUB C	SUB D	SUB E	SUB H	SUB L	SUB M	SUB A
23_	SBB B	SBB C	SBB D	SBB E	SBB H	SBB L	SBB M	SBB A
24_	ANA B	ANA C	ANA D	ANA E	ANA H	ANA L	ANA M	ANA A
25_	XRA B	XRA C	XRA D	XRA E	XRA H	XRA L	XRA M	XRA A
26_	ORA B	ORA C	ORA D	ORA E	ORA H	ORA L	ORA M	ORA A
27_	CMP B	CMP C	CMP D	CMP E	CMP H	CMP L	CMP M	CMP A
	0	1	2	3	4	5	6	7
30_	RNZ	POP B	JNZ	JMP	CNZ	PUSH B	ADI	RST 0
31_	RZ	RET	JZ	---	CZ	CALL	ACI	RST 1
32_	RNC	POP D	JNC	OUT	CNC	PUSH D	SUI	RST 2
33_	RC	---	JC	IN	CC	---	SBI	RST 3
34_	RPO	POP H	JPO	XTHL	CPO	PUSH H	ANI	RST 4
35_	RPE	PCHL	JPE	XCHG	CPE	---	XRI	RST 5
36_	RP	POP PSW	JP	DI	CP	PUSH PSW	ORI	RST 6
37_	RM	SPHL	JM	EI	CM	---	CPI	RST 7

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